7 #ifndef __MSP430WARE_EUSCI_A_UART_H__
8 #define __MSP430WARE_EUSCI_A_UART_H__
12 #ifdef __MSP430_HAS_EUSCI_Ax__
31 #define DEFAULT_SYNC 0x00
32 #define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55
39 typedef struct EUSCI_A_UART_initParam {
45 uint8_t selectClockSource;
47 uint16_t clockPrescalar;
66 uint16_t msborLsbFirst;
71 uint16_t numberofStopBits;
84 } EUSCI_A_UART_initParam;
93 #define EUSCI_A_UART_NO_PARITY 0x00
94 #define EUSCI_A_UART_ODD_PARITY 0x01
95 #define EUSCI_A_UART_EVEN_PARITY 0x02
103 #define EUSCI_A_UART_MSB_FIRST UCMSB
104 #define EUSCI_A_UART_LSB_FIRST 0x00
112 #define EUSCI_A_UART_MODE UCMODE_0
113 #define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE UCMODE_1
114 #define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE UCMODE_2
115 #define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE UCMODE_3
123 #define EUSCI_A_UART_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
124 #define EUSCI_A_UART_CLOCKSOURCE_ACLK UCSSEL__ACLK
132 #define EUSCI_A_UART_ONE_STOP_BIT 0x00
133 #define EUSCI_A_UART_TWO_STOP_BITS UCSPB
141 #define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01
142 #define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00
151 #define EUSCI_A_UART_RECEIVE_INTERRUPT UCRXIE
152 #define EUSCI_A_UART_TRANSMIT_INTERRUPT UCTXIE
153 #define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT UCRXEIE
154 #define EUSCI_A_UART_BREAKCHAR_INTERRUPT UCBRKIE
155 #define EUSCI_A_UART_STARTBIT_INTERRUPT UCSTTIE
156 #define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT UCTXCPTIE
166 #define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG UCRXIFG
167 #define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG UCTXIFG
168 #define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG UCSTTIFG
169 #define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG UCTXCPTIFG
178 #define EUSCI_A_UART_LISTEN_ENABLE UCLISTEN
179 #define EUSCI_A_UART_FRAMING_ERROR UCFE
180 #define EUSCI_A_UART_OVERRUN_ERROR UCOE
181 #define EUSCI_A_UART_PARITY_ERROR UCPE
182 #define EUSCI_A_UART_BREAK_DETECT UCBRK
183 #define EUSCI_A_UART_RECEIVE_ERROR UCRXERR
184 #define EUSCI_A_UART_ADDRESS_RECEIVED UCADDR
185 #define EUSCI_A_UART_IDLELINE UCIDLE
186 #define EUSCI_A_UART_BUSY UCBUSY
194 #define EUSCI_A_UART_DEGLITCH_TIME_2ns 0x00
195 #define EUSCI_A_UART_DEGLITCH_TIME_50ns UCGLIT0
196 #define EUSCI_A_UART_DEGLITCH_TIME_100ns UCGLIT1
197 #define EUSCI_A_UART_DEGLITCH_TIME_200ns (UCGLIT0 + UCGLIT1)
230 extern bool EUSCI_A_UART_init(uint16_t baseAddress,
231 EUSCI_A_UART_initParam *
param);
251 extern void EUSCI_A_UART_transmitData(uint16_t baseAddress,
268 extern uint8_t EUSCI_A_UART_receiveData(uint16_t baseAddress);
298 extern void EUSCI_A_UART_enableInterrupt(uint16_t baseAddress,
328 extern void EUSCI_A_UART_disableInterrupt(uint16_t baseAddress,
356 extern uint8_t EUSCI_A_UART_getInterruptStatus(uint16_t baseAddress,
380 extern void EUSCI_A_UART_clearInterrupt(uint16_t baseAddress,
396 extern void EUSCI_A_UART_enable(uint16_t baseAddress);
411 extern void EUSCI_A_UART_disable(uint16_t baseAddress);
447 extern uint8_t EUSCI_A_UART_queryStatusFlags(uint16_t baseAddress,
465 extern void EUSCI_A_UART_setDormant(uint16_t baseAddress);
480 extern void EUSCI_A_UART_resetDormant(uint16_t baseAddress);
495 extern void EUSCI_A_UART_transmitAddress(uint16_t baseAddress,
516 extern void EUSCI_A_UART_transmitBreak(uint16_t baseAddress);
530 extern uint32_t EUSCI_A_UART_getReceiveBufferAddress(uint16_t baseAddress);
544 extern uint32_t EUSCI_A_UART_getTransmitBufferAddress(uint16_t baseAddress);
561 extern void EUSCI_A_UART_selectDeglitchTime(uint16_t baseAddress,
562 uint16_t deglitchTime);
MPU_initThreeSegmentsParam param